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Chapter 14: AltLab Library
14–13
Signal Compiler
Use the Signal Compiler block to create and compile a Quartus II project for your
DSP Builder design, and to program your design onto an Altera ? FPGA.
1
You must save your model file before you can use the Signal Compiler block.
Table 14–16 shows the controls and parameters for the Signal Compiler block.
Table 14–16. Signal Compiler Block Parameters Settings Page
Name
Family
Use Board Block
to Specify Device
Compile
Scan JTAG
Program
Analyze
Synthesis
Fitter
Value
Stratix ? , Stratix GX,
Stratix II, Stratix II GX,
Stratix III, Stratix IV,
Arria ? GX, Arria II GX,
Cyclone ? , Cyclone II,
Cyclone III
On or Off
—
List of ports connected to
the JTAG cable.
—
—
—
—
Description
The Altera device family you want to target.
If you use the automated design flow, the Quartus II software
automatically uses the smallest device in which your design fits.
Turn on to get the device information from the development board block.
Click to compile your design.
The required JTAG cable port.
Click to download your design to the connected development board.
Click to analyze the DSP Builder system.
Click to run Quartus II synthesis.
Click to run the Quartus II Fitter tool.
Turn on to enable use of a SignalTap II Logic Analyzer block in your
Enable SignalTap II On or Off
design. Turn on this setting to add extra logic and memory to capture
signals in hardware in real time.
SignalTap II depth
SignalTap II clock
Use Base Clock
Export
2, 4, 8, 16, 32, 64, 128,
256, 512, 1k, 2K, 4K, 8K
User defined
On or Off
—
The required depth for the SignalTap II Logic Analyzer.
Specifies the clock to use for capturing data with the SignalTap II feature
from a list of available signals.
Turn on if you want to use the base clock for the SignalTap II Logic
Analyzer.
Exports synthesizable HDL to a user-specified directory.
1
Use a Clock or Clock_Derived block to specify the clock and reset signals.
SignalTap II Logic Analyzer
As programmable logic design complexity increases, system verification in software
becomes time consuming and replicating real-world stimulus is increasingly difficult.
To alleviate these problems, you can supplement traditional system verification with
efficient board-level verification.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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